1. Field of the Invention
The present invention generally relates to a non-volatile memory, and more particularly to a method of sorting a multi-bit per cell flash memory and a multi-mode configuration method for a multi-bit per cell flash memory.
2. Description of Related Art
Flash memory is a non-volatile solid state memory device that can be electrically erased and reprogrammed. Conventional flash memory stores a single bit of information in each memory cell such that each memory cell can be programmed to assume two possible states. The conventional flash memory is thus commonly referred to as single-bit per cell flash memory. Modern flash memory is capable of storing two or more bits of information in each memory cell such that each memory cell can be programmed to assume more than two possible states. The modern flash memory is thus commonly referred to as multi-bit per cell flash memory.
A multi-bit per cell flash memory chip, such as 3-bit per cell (3-bpc) flash memory, may ordinarily contain defective or bad blocks. Even though the bad blocks cannot be operated to the full in the 3-bpc mode, the flash memory may probably be operated in 2-bpc mode or in 1-bpc mode. As a result, the flash memory chip with defective block(s) need not be discarded. Whether the flash memory chip with defective block(s) is capable of being operated in lesser-bit per cell mode can be determined (or tested) by sorting, for example, via programming and reading the flash memory.
FIG. 1A shows a conventional page program/read sequence in a block for a 3-bpc flash memory, which performs page program/read in the following order:
00h→01h→02h→03h→04h→05h→06h→07h→ . . . BD h→BEh→BFh.
FIG. 1B illustrates a flow diagram of a conventional method of sorting a flash memory. According to the illustrated flow diagram, the flash memory is subjected to 3-bpc mode sorting (step 11), 2-bpc mode sorting (step 12) and 1-bpc mode sorting (step 13). Specifically speaking, in the 3-bpc mode sorting, all (192) pages including low-bit pages, mid-bit pages and high-bit pages (i.e., 00h→01h→02h→03h→04h→05h→ . . . BDh→BEh→BDh) are subjected to program/read. In the 2-bpc mode sorting, all (128) pages including low-bit pages and mid-bit pages (i.e., 00h→01h→02h→03h→04h→06h→07h→ . . . BAh→BBh→BDh) are subjected to program/read. In the 1-bpc mode sorting, all (64) low-bit pages (i.e., 00h→01h→03h→06h→ . . . BAh) are subjected to program/read. As a result, the low-bit pages are sorted (or tested) three times and the mid-bit pages are sorted two times.
For the reason that the conventional method could not effectively and economically sort a flash memory, a need has thus arisen to propose a novel scheme for sorting a multi-bit per cell flash memory.